555 Timer Datasheet and Calculator: NE555 Pinout, Astable and Monostable Circuits

The 555 is an 8-pin timer IC that runs one of two circuits: a monostable one-shot whose pulse width is tw = 1.1·RA·C, or an astable oscillator whose frequency is f = 1.44/((RA+2RB)·C). It works from 4.5 V to 16 V, sinks or sources up to 200 mA, and has been in production since 1973 — TI’s NE555 datasheet was revised again in March 2026. The calculator below solves both modes with the datasheet’s own formulas; the rest of this page is the datasheet, decoded.

555 Calculator

555 Timer Pin Configuration

Eight pins, numbered counterclockwise from the notch:

• 1 GND — ground reference
• 2 TRIG — starts timing; the output goes high when this pin is pulled below 1/3 VCC
• 3 OUT — the timer output; sinks or sources up to 200 mA
• 4 RESET — active low, overrides everything; tie to VCC when unused, or the timer false-triggers
• 5 CONT — direct access to the internal 2/3 VCC threshold node; decouple with 0.01 µF when unused
• 6 THRES — ends timing; the output goes low when this pin rises above 2/3 VCC
• 7 DISCH — open-collector transistor to ground, active while the output is low; this is what empties the timing capacitor
• 8 VCC — supply, 4.5 V to 16 V

The mode is set entirely by how TRIG, THRES, and DISCH are wired: tie THRES to DISCH and you have a one-shot; tie THRES to TRIG and you have an oscillator. Same die, two circuits.

555 Timer CAD Layout

PDIP-8 (P) uses two rows of pads on 2.54 mm pitch and a 7.62 mm row span; SOIC-8 (D) is a standard 1.27 mm-pitch surface-mount pattern. One layout rule matters more than any other with this part: keep the 0.01 µF CONT capacitor and the timing capacitor’s ground return short. The timing thresholds are ratios of VCC, so supply noise walks straight into the timing — a bypass capacitor at pin 8 is not optional in a clean design.

[DATASHEET DOWNLOAD BLOCK — NE555, TI official PDF: https://www.ti.com/lit/ds/symlink/ne555.pdf]

Overview and Analysis

The 555 predates almost everything else on a modern BOM — Signetics introduced it in 1973 — and TI’s current datasheet (SLFS022, Revision K) was updated in March 2026. Fifty-three years in production and a revision this year is the whole argument for the part: it is cheap, second-sourced, understood by everyone, and does not require firmware.

Two TI naming lines coexist and confuse part searches. NE555 descends from the Signetics part number; LM555 descends from National Semiconductor’s version and joined TI’s catalog through the 2011 acquisition. They are separate orderable parts with separate datasheets that do the same job with the same formulas. Add onsemi and Diodes Incorporated, which both build NE555-family parts of their own, and the 555 is one of the most genuinely multi-sourced ICs in existence — the opposite supply-chain situation from a single-source part like the LM35 covered earlier in this series.

What the 555 is not: precise. Timing accuracy hangs on the absolute values of external R and C, and the astable mode drifts at 150 ppm/°C typical. For clock-grade timing there are crystals and MCU timers; the 555’s territory is timing that needs to be cheap, robust, and visible on a schematic.

555 Timer Technical Specifications

Parameter	NE555
Supply voltage	4.5 V to 16 V
Supply current (VCC = 5 V, no load)	6 mA max
Supply current (VCC = 15 V, no load)	15 mA max
Output sink/source	up to 200 mA
Monostable pulse width	tw = 1.1·RA·C, minimum ≈10 µs
Recommended max frequency	100 kHz
Timing drift, monostable	50 ppm/°C typ
Timing drift, astable	150 ppm/°C typ
Supply sensitivity, monostable	0.1 %/V typ

Two numbers deserve a second look. The supply current — milliamps, not microamps — makes the bipolar 555 a poor battery citizen; that is a CMOS-variant problem to solve (below). And 4.5 V minimum means the NE555 is out of spec on every 3.3 V rail, the same trap the LM35 sets: an ESP32 or Pi Pico design needs either a 5 V supply for the timer or a CMOS 555 (TLC555, LMC555) that runs down to 2 V-class supplies and keeps the same pinout and formulas.

555 Family and Suffix Decoding

The part number encodes temperature grade and package. Grade first:

Grade	Temp range	Note
NE555	0°C to 70°C	the commercial default
SA555	−40°C to +85°C	industrial
NA555	−40°C to +105°C	extended industrial
SE555	−55°C to +125°C	military range, and 18 V max supply with tighter drift specs

Then package: P = PDIP-8 and D = SOIC-8 across the family; PS (SO-8) and PW (TSSOP-8) exist for the NE555 grade only; the SE555 adds ceramic (JG) and LCCC (FK). The part almost everyone means by “a 555” is the NE555P — commercial grade, through-hole PDIP. As with the LM35’s grade system, the headline temperature range belongs to a grade you probably didn’t order: a breadboard NE555P is a 0-to-70°C part, and below-freezing applications need the SA/NA/SE letters, not hope.

How the 555 Works

Inside are five things: a three-resistor divider that generates 1/3 VCC and 2/3 VCC references, two comparators, an SR latch, an output stage, and a discharge transistor.

The datasheet states the logic in two sentences worth quoting: when TRIG falls below the 1/3 VCC trigger level, the latch is set and the output goes high; when THRES rises above the 2/3 VCC threshold level (and TRIG is back above its level), the latch resets and the output goes low. While the output is low, the discharge transistor provides a low-impedance path from DISCH to ground.

Every 555 circuit is a choreography of those three events. The CONT pin exposes the 2/3 VCC node directly — inject a voltage there and both thresholds move, which turns the astable into a voltage-controlled oscillator and the monostable into a pulse-width modulator. That is also why the thresholds are ratios rather than absolute voltages: timing set by RC against a VCC-proportional threshold cancels VCC out of the timing equation, which is why the formulas below contain no supply term.

555 Timer Circuits

Monostable: one pulse of a set width

RA runs from VCC to the THRES/DISCH junction; C runs from there to ground; the trigger arrives on pin 2. Pull TRIG below 1/3 VCC and the output goes high while C charges through RA; when C reaches 2/3 VCC, the output drops and DISCH empties the capacitor. The pulse width:

tw = 1.1 · RA · C

One time constant to 63%, 1.1 time constants to the 2/3 mark — the 1.1 is not a fudge factor, it is ln(3) rounded. Boundaries from the datasheet: comparator storage time sets a practical minimum pulse of about 10 µs, and total timing resistance (RA here; RA + RB in astable mode) tops out around 3.4 MΩ at VCC = 5 V and 10 MΩ at 15 V, above which comparator bias current corrupts the charge curve. Within those rails the reachable range spans microseconds to minutes with sane component values.

Worked example — a 5-second delay: pick C = 10 µF, then RA = tw / (1.1 · C) = 5 / (1.1 × 10⁻⁵) ≈ 455 kΩ. The nearest standard value, 470 kΩ, gives tw = 1.1 × 470 kΩ × 10 µF = 5.17 s. That last step is the honest part of 555 design: you round to a resistor you can buy, and the timing moves with it — plus the tolerance of the capacitor, which for an aluminum electrolytic can be −20/+80%. Long delays deserve a film or C0G/NP0 ceramic timing capacitor; electrolytic leakage current competes with the charging current through a large RA and stretches or stalls the ramp.

Two behavioral details the formula hides. TRIG is level-sensitive, not edge-sensitive: the trigger pulse must be shorter than the intended output pulse, because holding pin 2 below 1/3 VCC keeps the output high regardless of what the capacitor does — a slow or stuck trigger reads as “my pulse width is wrong” on the bench. And during the pulse the basic circuit ignores new triggers; it is not retriggerable. A retriggerable one-shot (restarting the timing on every new event, as a watchdog needs) requires either extra components on DISCH or a different part.

Astable: a free-running oscillator

THRES ties to TRIG, so the capacitor’s own voltage retriggers the circuit forever: C charges through RA + RB to 2/3 VCC, discharges through RB alone to 1/3 VCC, repeat.

• tH = 0.693 · (RA + RB) · C
• tL = 0.693 · RB · C
• f = 1.44 / ((RA + 2RB) · C)
• duty = (RA + RB) / (RA + 2RB)

Look at the duty-cycle formula before reaching for the calculator: since the charge path (RA + RB) is always longer than the discharge path (RB), tH always exceeds tL — the basic astable cannot produce a duty cycle at or below 50%. It approaches 50% as RB grows much larger than RA, and approaches 100% as RA dominates. Most “my 555 duty cycle is wrong” questions are this structural property, not a broken chip. Genuinely symmetric or sub-50% output takes a modified circuit (a diode bypassing RB during charge is the usual route) or dividing a higher frequency by two.

Worked example — a 1 Hz indicator blink: pick C = 10 µF, so RA + 2RB must equal 1.44 / (1 Hz × 10 µF) = 144 kΩ. Choosing RB = 68 kΩ and RA = 8.2 kΩ gives RA + 2RB = 144.2 kΩ → f = 0.999 Hz, with duty = 76.2 / 144.2 ≈ 53% — close to a symmetric blink precisely because RB was made large relative to RA. Flip the proportions (RA = 130 kΩ, RB = 6.8 kΩ) and the same frequency budget produces a ~95% duty cycle: a short pop of LED-off once a second. The frequency formula fixes only the sum; how you split it between RA and RB is the duty-cycle dial.

The recommended operating region tops out around 100 kHz for the bipolar part. It will oscillate faster, but waveform quality and timing accuracy degrade; past that, the CMOS variants (rated into the MHz region) are the correct part, not a hotter-rodded RC pair. At the other extreme, the same maximum-resistance rails apply as in monostable mode — 3.4 MΩ total at 5 V — which with a quality low-leakage capacitor puts cycle times of minutes within reach, but pushes the circuit into territory where board leakage and humidity join the error budget.

Bistable and the RESET pin

With no timing capacitor at all, TRIG and RESET make the 555 a set/reset flip-flop with a 200 mA output — a debounced latch for a panel button costs one IC and two pull-ups. In every mode, unused RESET must go to VCC; a floating pin 4 is the classic source of phantom resets.

555 Timer Characteristics

The precision hierarchy inside the datasheet is worth reading as a design guide. Monostable mode drifts at 50 ppm/°C typical with 0.1 %/V supply sensitivity; astable mode drifts at 150 ppm/°C — three times worse, on the same die, because both the charge and discharge thresholds participate in every cycle. If a design needs the more stable number, structure it around a triggered one-shot rather than a free-runner. The SE555 grade tightens every one of these specs (30-100 ppm/°C monostable, 0.05-0.2 %/V) along with its wider temperature range — the military letter buys accuracy, not just range.

The output stage’s 200 mA rating carries a caveat: at 200 mA sink and VCC = 15 V, the saturation voltage reaches 2.5 V max — at full current the “low” is not very low, and the dissipation lives in the 555. Package thermals run from 98.5°C/W (PDIP) to 164.2°C/W (TSSOP) junction-to-ambient, which bounds how much of that 200 mA rating is usable continuously in a small package.

The two control pins have numbers worth keeping on hand. CONT floats at the internal 2/3 VCC node — 2.6 V to 4 V at a 5 V supply, 9 V to 11 V at 15 V — and anything driving it must both source and sink current against the internal divider; when it is not driven, the 0.01 µF bypass exists to keep supply noise off the threshold, and the datasheet’s own advice is to evaluate it per application rather than treat it as a ritual. RESET asserts somewhere between 0.3 V and 1 V — a genuinely low threshold, which is why a floating pin 4 picks up enough coupling to fire: it takes under a volt of induced noise to kill the output. Reset overrides both comparators and discharges the timing capacitor’s state through the output logic, so releasing it starts a cycle from known conditions rather than resuming mid-ramp.

555 Timer Applications

The classic application set — LED flashers, tone generators, delay-on relays, PWM drivers, missing-pulse detectors — all reduces to the two circuits above plus the CONT pin. A dimming LED driver is the astable with its duty cycle steered through CONT; a door-chime delay is the monostable with RA·C in seconds; a servo tester is the monostable retriggered at 50 Hz.

The honest 2026 question is when a 555 still beats a microcontroller that costs the same. The cases that survive: driving 200 mA directly with no firmware, no boot time, and no code to maintain; timing that must keep working at 105°C or 125°C ambient (NA/SE grades) where hobby MCU boards are out of spec; one-shot supervision of the MCU itself; and teaching — the 555 makes RC timing, comparators, and latches visible in a way no black-box chip does. What no longer makes sense is multi-channel or reprogrammable timing; the crossover to an MCU comes fast and the 556 dual package only delays it by one channel.

Manufacturer Information

The 555 is the rare part where multi-sourcing is real and current. TI alone ships two lineages (NE555/SA555/NA555/SE555 and the National-derived LM555); onsemi produces its LM555; Diodes Incorporated makes the NE555/SA555/NA555 family — all three appear with their own PDFs in the same search results, and all follow the same formulas. CMOS descendants are where the roadmap points for new designs: TI’s TLC555 runs from 2 V, draws microamps instead of milliamps, and reaches past 1 MHz, at the cost of the bipolar part’s 200 mA output muscle. For the classic part there is no lifecycle pressure in any direction — SLFS022 Revision K, dated March 2026, is not the datasheet of a part being retired.